When a dual-port memory is shared by two devices, such as an input-output (I/O) device and a digital signal processor (DSP), a conventional arrangement has had the devices access the memory in sequence. Although the memory is thus used full time, each device accesses it only half the time. If three devices were to share the memory, access would drop to only a third of the time for each of them and their respective performances would be decreased to a corresponding extent.
One way to increase both access time and performance, when only two devices share the memory, is to use an arrangement known as a "ping-pong" design. In such an arrangement, the dual-port memory is divided into two sections, and one device is accessing one section of the memory while the other device is accessing the other section of the memory. Thus, an I/O device accesses the first section during a first time segment while a DSP accesses the second. Then, during a second time segment, the I/O device accesses the second section while the DSP accesses the first. The process repeats itself during subsequent segments of time. This "ping-pong" arrangement is more efficient in that both the memory and the devices are working full time and there is no waiting requirement before either device is connected to the memory.
The nature of the problem would change significantly if three or more devices need access to the memory. In a "ping-pong" arrangement, with more than two devices requiring access to the memory, at least one device needs to be awaiting its turn at any given segment of time.